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NXP Semiconductors /MKW41Z4 /XCVR_ANA /BB_LDO_1

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Interpret as BB_LDO_1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)BB_LDO_ADCDAC_BYP 0 (0)BB_LDO_ADCDAC_DIAGSEL 0BB_LDO_ADCDAC_SPARE 0 (000)BB_LDO_ADCDAC_TRIM 0 (0)BB_LDO_BBA_BYP 0 (0)BB_LDO_BBA_DIAGSEL 0BB_LDO_BBA_SPARE 0 (0)BB_LDO_BBA_TRIM 0 (0)BB_LDO_FDBK_BYP 0 (0)BB_LDO_FDBK_DIAGSEL 0BB_LDO_FDBK_SPARE 0 (0)BB_LDO_FDBK_TRIM 0 (0)BB_LDO_HF_BYP 0 (0)BB_LDO_HF_DIAGSEL 0BB_LDO_HF_SPARE 0 (0)BB_LDO_HF_TRIM

BB_LDO_HF_TRIM=0, BB_LDO_ADCDAC_BYP=0, BB_LDO_FDBK_BYP=0, BB_LDO_BBA_DIAGSEL=0, BB_LDO_BBA_BYP=0, BB_LDO_FDBK_DIAGSEL=0, BB_LDO_BBA_TRIM=0, BB_LDO_ADCDAC_TRIM=000, BB_LDO_FDBK_TRIM=0, BB_LDO_HF_BYP=0, BB_LDO_ADCDAC_DIAGSEL=0, BB_LDO_HF_DIAGSEL=0

Description

RF Analog Baseband LDO Control 1

Fields

BB_LDO_ADCDAC_BYP

rmap_bb_ldo_adcdac_byp

0 (0): Bypass disabled.

1 (1): Bypass enabled
BB_LDO_ADCDAC_DIAGSEL

rmap_bb_ldo_adcdac_diagsel

0 (0): Diag disable

1 (1): Diag enable
BB_LDO_ADCDAC_SPARE

rmap_bb_ldo_adcdac_spare[1:0]
BB_LDO_ADCDAC_TRIM

rmap_bb_ldo_adcdac_trim[2:0]

0 (000): 1.20 V ( Default )

1 (001): 1.25 V

2 (010): 1.28 V

3 (011): 1.33 V

4 (100): 1.40 V

5 (101): 1.44 V

6 (110): 1.50 V

7 (111): 1.66 V
BB_LDO_BBA_BYP

rmap_bb_ldo_bba_byp

0 (0): Bypass disabled.

1 (1): Bypass enabled
BB_LDO_BBA_DIAGSEL

rmap_bb_ldo_bba_diagsel

0 (0): Diag disable

1 (1): Diag enable
BB_LDO_BBA_SPARE

rmap_bb_ldo_bba_spare[1:0]
BB_LDO_BBA_TRIM

rmap_bb_ldo_bba_trim[2:0]

0 (0): 1.20 V ( Default )

1 (1): 1.25 V

2 (2): 1.28 V

3 (3): 1.33 V

4 (4): 1.40 V

5 (5): 1.44 V

6 (6): 1.50 V

7 (7): 1.66 V
BB_LDO_FDBK_BYP

rmap_bb_ldo_fdbk_byp

0 (0): Bypass disabled.

1 (1): Bypass enabled
BB_LDO_FDBK_DIAGSEL

rmap_bb_ldo_fdbk_diagsel

0 (0): Diag disable

1 (1): Diag enable
BB_LDO_FDBK_SPARE

rmap_bb_ldo_fdbk_spare[1:0]
BB_LDO_FDBK_TRIM

rmap_bb_ldo_fdbk_trim[2:0]

0 (0): 1.2/1.176 V ( Default )

1 (1): 1.138/1.115 V

2 (2): 1.085/1.066 V

3 (3): 1.04/1.025 V

4 (4): 1.28/1.25 V

5 (5): 1.4/1.35 V

6 (6): 1.55/1.4 V

7 (7): 1.78/1.4 V
BB_LDO_HF_BYP

rmap_bb_ldo_hf_byp

0 (0): Bypass disabled.

1 (1): Bypass enabled
BB_LDO_HF_DIAGSEL

rmap_bb_ldo_hf_diagsel

0 (0): Diag disable

1 (1): Diag enable
BB_LDO_HF_SPARE

rmap_bb_ldo_hf_spare[1:0]
BB_LDO_HF_TRIM

rmap_bb_ldo_hf_trim[2:0]

0 (0): 1.20 V ( Default )

1 (1): 1.25 V

2 (2): 1.28 V

3 (3): 1.33 V

4 (4): 1.40 V

5 (5): 1.44 V

6 (6): 1.50 V

7 (7): 1.66 V

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of the copyright holder nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data